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ARD2
1.00 for Rev B. Hardware
Airbag Reference Demonstrator using MPC5604P
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Clock Generation Module. More...
Functions | |
| void | vfnClockOutputEnable (CGMCLKOutConfig_t tMyCGMConfig) |
| Given that P[22] is enabled, this function enables or disables output of a clock signal to the CLKOUT pin. | |
| uint8_t | u8fnClockPLLConfig (uint8_t u8PLLInstance, uint8_t u8IDF, uint8_t u8ODF, uint8_t u8LDF) |
| This function allows to configure a PLL setting in order to change the frequency of the system bus (or any other). It responds to the formula (Fosc * LDF) / (IDF * ODF). | |
| void | vfnClockClearPLLFlag (uint8_t u8PLLInstance) |
| This function clears any existing PLL faults for a given instance. | |
Clock Generation Module.
Copyright (c) 2011 Freescale Semiconductor Freescale Confidential Proprietary
History:
| uint8_t u8fnClockPLLConfig | ( | uint8_t | u8PLLInstance, |
| uint8_t | u8IDF, | ||
| uint8_t | u8ODF, | ||
| uint8_t | u8LDF | ||
| ) |
This function allows to configure a PLL setting in order to change the frequency of the system bus (or any other). It responds to the formula (Fosc * LDF) / (IDF * ODF).
| u8PLLInstance,: | Either 0 or 1, depending on which PLL we're config u8IDF: IDF value in the formula. Can't be bigger than 4 bits. u8ODF: IDF value in the formula. Can't be bigger than 2 bits. u8LDF: IDF value in the formula. Can't be bigger than 7 bits. |
| void vfnClockClearPLLFlag | ( | uint8_t | u8PLLInstance | ) |
This function clears any existing PLL faults for a given instance.
| u8PLLInstance,: | Either 0 or 1, depending on which PLL we're config |
| void vfnClockOutputEnable | ( | CGMCLKOutConfig_t | tMyCGMConfig | ) |
Given that P[22] is enabled, this function enables or disables output of a clock signal to the CLKOUT pin.
| tMyCGMConfig,: | Contains enable/disable information, as well as the divisor value (1, 2, 4, 8) and the source (IRC, XTAL, PLL0 or PLL1) as defined by CGMCLKOutConfig_t. |